1. Field of the Invention
This invention relates generally to digital signal processors including digital filters and, more particularly, to a multiplier for use in such digital filter and to low-power addressing circuits for addressing a memory used in the digital signal processor.
2. Description of the Background
Great strides have been recently made in increasing the density of the circuits implemented on integrated circuit chips and to increasing the speed with which such chips can operate. Systems that were heretofore thought too large to be incorporated into a single integrated circuit chip have now been fabricated as integrated circuits. For example, digital signal processors have now been implemented as integrated circuits, generally using the CMOS technology. Thus, the emphasis so far has been on increasing the density, that is, increasing the number of transistors that can be provided on an integrated circuit chip and to increasing the so-called throughput, that is, the speed with which data can be manipulated or processed. Integrated circuit chips are generally provided in systems that have relatively unlimited power supplies, that is, operated either from large solar cells and battery combinations or from standard AC mains. The problem now arises that in some applications for these high-density, sophisticated integrated circuit chips the power supplies have not kept pace with the integrated circuit technology. Thus, applications arise in which designers wish to use sophisticated integrated circuits but do not have sufficient battery power to use such circuits. For example, a watch or a hearing aid might be a suitable application for a digital signal processing system but the power available from the batteries is insufficient to provide a commercially acceptable product.
In regard to digital signal processors, they are typically embodied by a digital finite impulse response (FIR) filter that is commonly known to include one or more multipliers, an accumulator, a memory for coefficient storage, and some delay circuit or memory to store previous input words. As is known, these multipliers tend to be the most power consuming of all of the circuit elements in the digital FIR filter. As noted above, the CMOS technology is generally favored for high density integrated circuits of this kind, and it is known that the power dissipation of a CMOS circuit is given generally by the following equation: P=CV.sup.2 F, where V.sup.2 is the supply voltage times the voltage swing between circuit states, C is the output load capacitance when the circuit is a simple gate, and F is the clock frequency. Because a digital FIR filter may include a large number of multipliers, the capacitance value is quite high or if the multipliers are connected so that they may be used repeatedly and thereby reduce the required number, the clock frequency will be increased to a high rate. Therefore, it is seen that the multiplier is one of the single most power hungry elements in the digital FIR filter.
Another area in the digital signal processor in which power consumption may be reduced is in the addressing of both the memory that stores the coefficients used to achieve the desired transfer function and the memory that stores the delayed data samples in the digital FIR filter. If a random access memory (RAM) is employed then it is traditionally addressed using a binary counter. This addressing system utilizes more power than the methods in this invention for addressing in low-power battery applications.